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Thursday, August 21 • 2:30pm - 3:20pm
Open Innovation with IBM and The OpenPower Foundation's Coherent Accelerator Processor Interface - Brian Zoric & JT Kellington, IBM

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Brian Zoric and JT Kellington from IBM  will be presenting the knowledge required to create innovative computing solutions based around the POWER8 I/O protocol known as  "Coherent Accelerator Processor Interface" (or CAPI for short).  A CAPI connected device hooked up to a POWER8 microprocessor creates a "hollow core", or programmable processor, that can dramatically accelerate any data-intensive workload you can imagine. This technology opens the door to innovation from the industry and academia in a profound manner. We have barely scratched the surface of what is possible with this new technology. Specific CAPI coding examples will be discussed showing its ease of use, and attendees will exit the talk equipped with the knowledge that they need to immediately start  innovating with this new technology. 

This talk will outline what CAPI is , some ways it has been used in the lab and will cover some specific scenarios and proof points showing the end user benefits from this exciting new acceleration technology.  In addition, specific CAPI coding examples will be discussed showing the  ease of use of the technology. Attendees will exit the talk equipped with the knowledge that they need to immediately start innovating with this new technology.

Speakers
JJ

Jeffrey (JT) Kellington

JT Kellington is currently the Coherent Accelerator Processor Interface (CAPI) lab lead for the IBM POWER Systems design team. He is also actively contributing to the development and debug of the Linux kernel stack for CAPI enablement in POWER systems. He graduated from the University of Illinois in 2001 with his B.S. in Computer Engineering. He started with IBM in 2002 and has held various pre- and post-silicon verification roles since.
BZ

Brian Zoric

Brian Zoric currently manages the executive briefing centers in both Austin, TX and Rochester, MN. Previously Brian managed the Chief Architects and Chief Engineers of all POWER Systems. Prior career roles have included chip integration, circuit design and computer aided design tool development and management. Brian graduated from the University of Pittsburgh with a B.S.E.E in 1990.


Thursday August 21, 2014 2:30pm - 3:20pm
Sheraton Ballroom V

Attendees (10)